In order to enhance the processing throughput of microprocessors, processors may hold data in a series of caches. To use these caches in a multi-processor environment, various cache-coherency protocols have evolved. These cache-coherency schemes may associate an attribute, called a cache-coherency state, with various cache lines in the caches. A common cache-coherency protocol is what may be called the “Illinois Protocol”, also informally called the MESI (modified/exclusive/shared/invalid) protocol, where each cache line may be associated with one of the four MESI states. Other common cache-coherency protocols may include additional states. In this way, multiple copies of a given cache line, perhaps modified, may exist among the various caches in a multi-processor system in a predictable and coherent manner.
The existing MESI states may possess certain performance-limiting attributes. In one situation, when a modified cache line in a inner-level cache (e.g. level 1 cache) wishes to become invalid and write its modified data up to an outer-level cache (e.g. level 2 cache), the outer-level cache may in turn become invalid and write its modified data to an even more outer-level cache or to system memory. This may not be advantageous if there is significant traffic on the outer-level interfaces. In another situation, when a snoop request arrives at an outer-level cache, it must be sent down to any inner-level caches. This may not be advantageous if there is significant use of the inner-level caches over the inner-level interfaces.